1. Field of the Invention
This invention relates to signal level shift circuits that shift signal levels between different electric circuit systems operating based on different supply voltages, so that signals of one circuit system are converted to be suitable for another circuit system.
2. Description of the Related Art
FIG. 4A shows a typical example of the configuration of a signal level shift circuit, which receives an input signal xe2x80x98INxe2x80x99 whose level is 3V to provide an output signal xe2x80x98OUTxe2x80x99 whose level is 5V. That is, the overall configuration of FIG. 4A contains a VDDL circuit system operating based on a relatively low supply voltage VDDL of 3V, and a VDDH circuit system operating based on a relatively high supply voltage VDDH of 5V. The VDDL circuit system comprises inverters IV1 and IV2 for producing complementary signals with respect to the input signal IN. The VDDH circuit system comprises a level shift circuit LS, which forms a main part of the signal level shift circuit, and an inverter IV3 for waveform shaping.
Specifically, the VDDL circuit system has a CMOS (i.e., Complementary Metal-Oxide Semiconductor) configuration consisting of the inverters IV1 and IV2, which operate based on the supply voltage VDDL of 3V. Herein, the inverter IV1 is supplied with the input signal IN from an external device (not shown), and the output terminal thereof is connected to the input terminal of the inverter IV2. That is, the inverter IV1 outputs an inverse phase signal (or inversion signal) of the input signal IN, while the inverter IV2 outputs a same phase signal of the input signal IN.
The level shift circuit LS comprises a load circuit portion consisting of p-channel metal-oxide field-effect transistors (hereinafter, referred to as PMOS transistors) TP1 and TP2, and a drive circuit portion consisting of n-channel metal-oxide semiconductor field-effect transistors (hereinafter, referred to as NMOS transistors) TN1 and TN2, wherein the load circuit portion is driven by the drive circuit portion. The sources of the PMOS transistors TP1 and TP2 are commonly connected with the voltage supply VDDH of 5V. In addition, the gates and drains of the PMOS transistors TP1 and TP2 are alternately connected to each other. That is, the gate of the PMOS transistor TP1 is connected with the drain of the PMOS transistor TP2, and the gate of the PMOS transistor TP2 is connected with the drain of the PMOS transistor TP1.
The drain of the NMOS transistor TN1 is connected to the drain of the PMOS transistor TP1 via a node Na, and the drain of the NMOS transistor TN2 is connected to the drain of the PMOS transistor TP2 via a node Nb. In addition, the sources of the NMOS transistors TN1 and TN2 are both grounded. The gate of the NMOS transistor TN1 is supplied with the inverse phase signal of the input signal IN from the inverter IV1. The gate of the NMOS transistor TN2 is supplied with the same phase signal of the input signal IN from the inverter IV2. That is, the gates of the NMOS transistors TN1 and TN2 are respectively supplied with complementary signals, which are complementary to each other.
The node Nb that is established between the drains of the PMOS transistor TP2 and the NMOS transistor TN2 is connected to the input terminal of the inverter IV3 having a CMOS configuration, which operates based on the prescribed voltage of 5V. Therefore, the inverter IV3 provides the output signal OUT, which is an inverse signal of a signal appearing at the node Nb.
The inverters IV1 and IV2 of the VDDL circuit system, and the level shift circuit LS and inverter IV3 of the VDDH circuit system are all given the same ground potential of 0V, which is the reference potential in measurement of signal levels in the VDDL circuit system and VDDH circuit system. That is, the VDDL circuit system receiving the input signal IN has the prescribed signal level of 3V based on the reference ground potential, and the VDDH circuit system providing the output signal OUT has the prescribed signal level of 5V based on the reference ground potential.
Next, the overall operation of the signal level shift circuit of FIG. 4A will be described with reference to FIG. 4B.
When the input signal IN is low (i.e., 0V) in the VDDL circuit system, the inverter IV1 outputs a signal whose level is 3V, and the inverter IV2 outputs a signal whose level is 0V. In the VDDH circuit system, the NMOS transistor TN1 whose gate receives the output signal of the inverter IV1 is turned on, while the NMOS transistor TN2 whose gate receives the output signal of the inverter IV2 is turned off.
Due to the ON state of the NMOS transistor TN1, the node Na is pulled down to a low level, so that the PMOS transistor TP2 whose gate is connected with the node Na is turned on. At this time, the NMOS transistor TN2 is turned off while the node Nb is pulled up to a high level (5V), so that the PMOS transistor TP1 whose gate is connected with the node Nb is turned off. The inverter IV3 receives the high level (5V) of the node Nb to provide the output signal OUT having a low level.
In contrast, when the input signal IN is high (i.e., 3V) in the VDDL circuit system, the inverter IV1 outputs a signal whose level is 0V while the inverter IV2 outputs a signal whose level is 3V. In this case, the NMOS transistor TN1 is turned off while the NMOS transistor TN2 is turned on. As a result, the node Nb is pulled down to the low level (0V), so that the IV3 operating based on the low-level potential of the node Nb outputs a high-level signal OUT of 5V.
As described above, the signal level circuit of FIG. 4A works in such a way that the input signal whose level is 3V is converted to the output signal OUT whose level is 5V. Thus, it is possible to realize communication of signals between different circuit systems that operate based on different supply voltages respectively.
With respect to the PMOS transistor TP1 and the NMOS transistor TN1 that are connected in series between the power supply VDDH and the ground, the PMOS transistor TP1 is turned off during the period in which the input signal IN is low (0V), while the NMOS transistor TN1 is turned off during the period in which the input signal IN is high (3V). Therefore, there may be no possibility that a through current flows between the power supply VDDH and the ground via these transistors. Similarly, with respect to the PMOS transistor TP2 and the NMOS transistor TN2 that are connected in series between the power supply VDDH and the ground, one of these transistors is selectively turned off, which may indicate no possibility that a through current flows between the power supply VDDH and the ground via these transistors. That is, as long as the input signal IN is securely set to the high or low level, it is possible to reliably secure conversion of signal levels between different circuit systems without causing through currents to flow in the level shift circuit LS.
However, there still remains a problem in that through currents occur and flow in the level shift circuit LS supplied with the supply voltage VDDH when reduction occurs in the supply voltage VDDL.
Next, a description will be given with respect to the mechanism of occurrence of through currents in the level shift circuit LS. In the level shift circuit LS, as long as one of the NMOS transistors TN1 and TN2 is securely turned off, the PMOS transistors TP1 and TP2 are each complementarily turned on in association with the NMOS transistors TN1 and TN2, so that no through current occur in the level shift circuit LS.
For some reason, however, when both the NMOS transistors TN1 and TN2 are temporarily turned on, both the nodes Na and Nb are simultaneously reduced in potentials, so that both the PMOS transistors TP1 and TP2 alternately connected with these nodes are simultaneously turned on. As a result, all the PMOS transistors TP1 and TP2, and the NMOS transistors TN1 and TN2 are simultaneously turned on, so that through currents occur and flow between the voltage supply VDDH and the ground.
The situation in which both the NMOS transistors TN1 and TN2 are simultaneously turned on may happen when a reduction occurs in the supply voltage VDDL so that the outputs of the inverters IV1 and IV2 become unstable or uncertain. That is, when reduction occur in the supply voltage VDDL, due to gate threshold voltages of MOS transistors, both the PMOS transistor and NMOS transistor forming each of the inverters IV1 and IV2 may be simultaneously turned off. As a result, the output signals of the inverters IV1 and IV2 become unstable or uncertain; in some cases, both of them become simultaneously high so that the NMOS transistors TN1 and TN2 will be simultaneously turned on. Such a phenomenon may frequently occur when the supply voltage VDDL is reduced close to the gate threshold voltages (e.g., 0.5V) of the MOS transistors forming the inverters IV1 and IV2.
It is an object of the invention to provide a signal level shift circuit that causes no through current flowing therethrough even when a reduction occurs in the supply voltage supplied to the input-side circuitry.
A signal level shift circuit of this invention realizes signal level conversion between different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion and a drive circuit portion, which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).
Specifically, the input-side circuit system operating based on the first supply voltage (VDDL) contains a first inverter for inputting the input signal (IN) and a second inverter for inputting the output of the first inverter in addition to the supply voltage detection circuit, while the output-side circuit system operating based on the second supply voltage (VDDH) contains the level shift circuit, flip-flop, and switch circuit. Herein, the drive circuit portion drives the load circuit portion in response to the outputs of the inverters, which are complementary to each other in relation to the input signal. The switch circuit breaks the current paths when the supply voltage detection circuit detects a reduction of the first supply voltage.
The supply voltage detection circuit comprises a PMOS transistor that operates based on the first supply voltage and whose gate is grounded, and a resistor by which the drain of the PMOS transistor is grounded.
In addition, the load circuit portion comprises a pair of PMOS transistors that operate based on the second supply voltage and whose gates and drains are alternately coupled together, while the drive circuit portion comprises a pair of NMOS transistors whose drains are respectively connected with the drains of the pair of the PMOS transistors. The switch circuit comprises an NMOS transistor whose drain is connected respectively with the sources of the pair of the NMOS transistors, whose source is grounded, and whose gate is connected with a node between the drain of the PMOS transistor and the resistor in the supply voltage detection circuit.
Alternatively, the switch circuit comprises a pair of NMOS transistors whose drains are respectively connected with the sources of the pair of the NMOS transistors, whose sources are grounded, and whose gates are commonly connected with a node between the drain of the PMOS transistor and the resistor in the supply voltage detection circuit.